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OKI Semiconductor ML7041
Audio CODEC
FEDL7041-04
Issue Date: Mar. 2, 2006
GENERAL DESCRIPTION
The ML7041 is a single-channel full duplex CODEC LSI device which performs mutual transcoding between the analog voice band signals ranging from 300 to 3400 Hz and the 64 kbps PCM serial data. Provided with such functions as DTMF Tone generation, transmit/receive data gain control, side-tone path, and low-dropout regulator, the ML7041 is best suited for telephone terminals in digital wireless systems.
FEATURES
* * * * * * * * Single 3 V power supply VDD: 2.4 to 3.3 V Coding format: PCM -law/PCM A-law/14-bit linear mode selectable PCM interface timing: Long frame synchronous timing/short frame synchronous timing selectable Transmit/receive full-duplex operation Serial PCM transmission data rate: 64 to 2048 kbps Low power consumption Operating mode: 15 mW typ. (VDD = 3.0 V) Power-down mode: 3 W typ. (VDD = 3.0 V) Master clock frequency: 2.048 MHz (compatible with PCM shift clock) Analog output stage 100 mW (differential type) amplifier output for driving receiver speaker: Capable of driving an 8 load. 6.6 mW (single type) amplifier output for driving earphones speaker: Capable of driving a 32 load. Built-in two low-dropout regulators (150 mA x 2) Built-in four general purpose drivers (150 mA x 4) Transmit/receive mute, transmit/receive programmable gain control Built-in side tone path Built-in DTMF tone generator Transmit slope filter selectable I2C bus interface (MCU interface) Built-in transmit voice signal detector Package: 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (ML7041 TB)
* * * * * * * * *
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BLOCK DIAGRAM
SWC SWB SWA
MIC1I MIC1O MIC2I MIC2O MIC3- MIC3+ MIC3O
20 k D/A 20 k CR1-B7,6 CR3-B7,6,5 20 k CR1-B1 CR0-B2 A/D
Slope Filter
VDD
Voice detect CR4-B6
PCM Com-p and
CR0-B0
PCMOUT
BPF BCLK
TONE/DTMF Gen CR3-B3,2,1,0 CR0-B0 CR2-B2,1,0
PCM Expand
SYNC
LPF
PCMIN
EAR1O
32
Regulator1 (150 mA)
RG1IN (3.6 V) RG1O (3.0 V) RG1PDN (3.0 V/0 V) RG2IN (3.6 V) RG2O (3.0 V) RG2PDN (3.0 V/0 V)
Sign bit EAR2O
32 20 k CR1-B5,4
Regulator2 (150 mA)
CR5-B7
GP1 (150 mA) GP2 (150 mA)
SG
VREF 8 8
MCU I/F 2 (I C)
CR5-B3,2,1,0
GP3 (150 mA) GP4 (150 mA) AGGP
SPO-
SPO+
EXTI
MCK
SCL
EXTO
SDA
PDN
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PIN CONFIGURATION (TOP VIEW)
MIC3O
MIC2O
MIC1O
MIC3+
MIC3-
MIC2I
MIC1I
SWC
SWB
39
SWA
38
SG
48
47
46
45
44
43
42
41
40
AG EAR2O EAR1O VA1 EXTO EXTI VA2 SPO- AG2
1 2 3 4 5 6 7 8 9
37
VA
36 35 34 33 32 31 30 29 28 27 26 25
RG2IN RG2O AGR2 RG1IN RG1O AGR1 RG2PDN RG1PDN PDN SYNC BCLK DG
AG3 10 SPO+ 11 VA3 12 AGGP1 13 GP1 14 GP2 15 GP3 16 GP4 17 AGGP2 18 VDD 19 MCK 20 SDA 21 SCL 22 PCMIN 23 PCMOUT 24
48-Pin Plastic TQFP
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PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol AG EAR2O EAR1O VA1 EXTO EXTI VA2 SPO- AG2 AG3 SPO+ VA3 AGGP1 GP1 GP2 GP3 GP4 AGGP2 VDD MCK SDA SCL PCMIN PCMOUT DG BCLK SYNC PDN RG1PDN RG2PDN AGR1 RG1O RG1IN AGR2 RG2O RG2IN VA SWA SWB SWC MIC1I MIC1O MIC2I MIC2O MIC3+ MIC3- MIC3O SG Type -- O O -- O I -- O -- -- O -- -- O O O O -- -- I I/O I I O -- I I I I I -- O I -- O I -- I/O I/O I/O I O I O I I O O Description Analog ground (0 V) Receive side voice amplifier output 2 Receive side voice amplifier output 1 Analog power supply 1 (3.0 V) Receive side voice amplifier output Receive side voice amplifier input Analog power supply 2 (3.0 V) Receive side voice amplifier output- Analog ground 2 (0 V) Analog ground 3 (0 V) Receive side voice amplifier output+ Analog power supply 3 (3.0 V) General purpose port ground 1 (0 V) General purpose port 1 output (Open drain) General purpose port 2 output (Open drain) General purpose port 3 output (Open drain) General purpose port 4 output (Open drain) General purpose port ground 2 (0 V) Digital power supply (3.0 V) Master clock input (2.048 MHz) I2C data input/output (Pull-up resister required) I2C shift clock input PCM receive signal input PCM transmit signal output Digital ground (0 V) PCM data shift clock input PCM data shift sync signal input Power down control input Power down input for regulator 1 (3.0 V/0 V) Power down input for regulator 2 (3.0 V/0 V) Ground for regulator 1 (0 V) Regulator 1 output (3.0 V) Regulator 1 power input (3.6 V) Ground for regulator 2 (0 V) Regulator 2 power output (3.0 V) Regulator 2 input (3.6 V) Analog power supply (3.0 V) Analog switch A Analog switch B Analog switch C Transmit side amplifier 1 inverting input Transmit side amplifier 1 output Transmit side amplifier 2 inverting input Transmit side amplifier 2 output Transmit side amplifier 3 non-inverting input Transmit side amplifier 3 inverting input Transmit side amplifier 3 output Analog signal ground (1.4 V) State in power-down mode -- High impedance High impedance -- High impedance -- -- High impedance -- -- High impedance -- -- High impedance High impedance High impedance High impedance -- -- -- High impedance -- -- "H" -- -- -- "L" "L" "L" -- "L" (RG1PDN = "L") -- -- "L" (RG2PDN = "L") -- -- -- -- -- -- High impedance -- High impedance -- -- High impedance "L"
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PIN AND FUNCTIONAL DESCRIPTIONS
MIC1I, MIC1O, MIC2I, MIC2O, MIC3-, MIC3+, MIC3- Transmit analog inputs and outputs for transmit gain adjustment. Gains of input levels of the pins can be adjusted using external resisters. MIC1I, MIC2I, and MIC3- are connected to the inverting inputs of the internal transmit amplifiers. MIC3+ is connected to the non-inverting input of the internal transmit amplifier 3. MIC1O, MIC2O, and MIC3O are connected to the internal transmit amplifier outputs. Analog input signals are controlled by the control register (CR1-B7, B6). Also, the amplifiers that are not being selected are deactivated and their outputs are put into high impedance state. Refer to Figure 1 for gain adjustment. EAR1O, EAR2O, EXTO, EXTI, SPO-, SPO+ Receive analog outputs and inputs for receive gain adjustment. EAR1O, EAR2O, and EXTO are the receive filter outputs. EAR1O and EAR2O can directly drive a 32 load. SPO+ and SPO- are differential analog signal outputs which can directly drive an 8 load. The receive side signal outputs can be selected by CR1-B5 and CR1-B4. If the amplifiers connected to EAR1O and EAR2O are not being selected, the amplifiers are deactivated and their outputs are put into high impedance state. Gains of output levels of the pins can be adjusted using the external resistors. The power control is accomplished by CR0-B6. Refer to Figure 1.
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Vi
C
R1 C R2
MIC1I MIC1O MIC2I C R4 MIC2O
20 k
Transmit Gain : VMIC1O/Vi = (R2/R1) : VMIC2O/Vi = (R4/R3) : VMIC3O/Vi = (R6/R5) A/D Input select :CR1-B7, B6 "00" -> MIC1 :CR1-B7, B6 "01" -> MIC2 :CR1-B7, B6 "10" -> MIC3 :CR1-B7, B6 "11" -> no-input Receive Gain :Vspo/VEXTO = (R8/R7) x 2 Output select :CR1-B5, B4 "00" -> EXTO :CR1-B5, B4 "01" -> EAR1O :CR1-B5, B4 "10" -> EAR2O :CR1-B5, B4 "11" -> no-output
Vi
C
R3
20 k
Vi
C
R5
MIC3- C R6 MIC3+ MIC3O SG
20 k
VREF
EAR1O
EAR2O
D/A
VEXTO R7
EXTO
EXTI R8 SPO-
C
VSPO SPO+
Figure 1 Analog Interface
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SG Analog signal ground. The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors 0.1 F ceramic type between this pin and GND to get the specified noise characteristics. During power-down, this output voltage is 0 V. SWA, SWB, SWC Used for an internal analog switch. The pin SWB is connected to the pin SWA or the pin SWC. This is controlled by CR1-B1. RG1PDN, RG1IN, RG1O Used for Regulator 1. The RG1PDN pin is a power down input. When set to "L", the Regulator 1 changes to the power down state. Since the power down is controlled by a logical OR with CR5-B4 of the control register, set CR5-B4 to logic "0" when using this pin. The RG1IN pin is input to the Regulator 1. The RG1O pin is output from the Regulator 1, whose voltage is 3.0 V. A 1 F ceramic type bypass capacitor must be connected between the power input pin and GND, and a 10 F tantalum bypass capacitor must be connected from the output pin to GND. RG2PDN, RG2IN, RG2O Used for Regulator 2. The RG2PDN pin is a power down input. When set to "L", the Regulator 2 changes to the power down state. Since the power down is controlled by a logical OR with CR5-B5 of the control register, set CR5-B5 to logic "0" when using this pin. The RG2IN pin is the input to the Regulator 2. The RG2O pin is the output from the Regulator 2, whose voltage is 3.0 V. A 1 F ceramic type bypass capacitor must be connected between the power input pin and GND, and a 10 F tantalum bypass capacitor must be connected from the output pin to GND. Note1: The RG1O and RG2O outputs must not be used as the 3 V supply for the ML7041. Note2: The RG1IN and RG2IN should be common near the device and supplied from the same power supply. GP1, GP2, GP3, GP4 General purpose driver output. Each pin is controlled by CR5-B1 through CR5-B4. By selecting CR5-B7, the GP1 pin can be controlled by the receive side sign bit. VDD, VA, VA1, VA2, VA3 VDD is the digital power supply. VA, VA1, VA2, and VA3 are the analog power supply pins. Since these pins are separated in the device, connect them as close as possible on the PCB. DG, AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1, AGGP2 Ground. DG is the digital ground. AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1 and AGGP2 are the analog ground. Since these pins are separated in the device, connect them as close as possible on the PCB. PDN Power down and reset control input. When set to digital "L", the device changes to the power down state and the control register is reset. Since the power down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic "0" when using this pin. The reset pulse width must be 200 ns or more. Be sure to reset the control register after turning on the power. MCK Master clock input. The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK. If a frequency of BCLK is 2.048 MHz, the BCLK can be shared with MCK. BCLK Shift clock input for the PCM data. The frequency is set in the range of 64 kHz to 2048 kHz for A/-law PCM data and set in the range of 128 kHz to 2048 kHz for linear code selection.
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SYNC 8 kHz synchronous signal input for transmit and receive PCM data. Synchronize this signal with BCLK signal. This signal is used to indicate the MSB of the PCM data stream. PCMOUT Transmit PCM data output. The PCM output signal is output from MSB, synchronously with the rising edges of BCLK and SYNC. Refer to Figure 2. This is a logic output pin so that external pull-up is not required. This pin outputs logic "L" except during effective PCM data bits, and outputs logic "H" during power-down. PCMIN Receive PCM data input. The PCM input signal is shifted in on the falling edge of BCLK and is input from MSB.
8 kHz (125 s)
SYNC BCLK PCMIN or PCMOUT MSB
LSB * 14 bits when linear mode is selected (a) Long frame synchronous interface
Refer to Figure 2.
8 kHz (125 s) SYNC BCLK PCMIN or PCMOUT
MSB
LSB * 14 bits when linear mode is selected (b) Short frame synchronous interface
Figure 2 PCM Interface Basic Timing Diagram
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SDA, SCL SDA is the serial data input/output pin and SCL is the serial clock line input pin. A pull-up register of 1 to 10 k is required for the SDA pin. The master clock is required when data is written or read. Transfer format The control register can be controlled according to the I2C bus transfer format. The control register address is 3 bits long and the register data is 8 bits long. The methods of writing and reading of data are shown below.
SDA SCL
A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
S
7-bit slave address "0011010"
R/W "0"
A
read-back mode bit "0"
register address
register data
A
A
P
slave address write
register address write
2
register data write
Figure 3 I C Interface Write Timing
SDA SCL
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
S
slave R/W address "0"
A
read-back mode bit "0"
register address
A
Sr
slave R/W address "1"
register data
A
register data read
A
P
slave address write
register address write
2
slave address write
Figure 4 I C Interface Read Timing: normal mode
SDA SCL
A2 A1 A0
B7 B6
B1 B0
B7 B6
B1 B0
S
slave R/W address "0"
A
slave address write
read-back mode bit "1"
register address
register data
register data
A
A
register data write
A
register data read
P
register address write
Figure 5 I C Interface Read Timing: read-back mode
ML7041 Slave address "0011010" S START condition P STOP condition Sr Repeated START condition
2
A Acknowledged (ML7041 drive SDA to "0")
A Not Acknowledged
Don't care ("0" or "1")
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Table 1 shows the register map. Table 1 Control Register Map
Name CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B7 A/ SEL MIC SEL1 B6 SPOUT PON Control and Detect Data B5 B4 B3 B2 SLP -- B1 SLP SEL SW C/A RX GAIN1 TONE GAIN1 B0 LNR RW R/W
PDN ALL PDN TX PDN RX SHORT FRAME
MIC SEL0 SP SEL1 SP SEL0
RX PAD R/W RX GAIN0 TONE GAIN0 R/W R/W R/W R/W R/W R
TX TX TX GAIN2 TX GAIN1 ON/OFF GAIN0
SIDE TONE SIDE TONE SIDE TONE
RX RX ON/OFF GAIN2 TONE GAIN3 TONE GAIN2
GAIN2 DTMF/ OTHERS SEL GP1 SEL CR/TONE
GAIN1 TONE SEND --
GAIN0 --
TONE ON/OFF TONE4
TONE3 TONE2 TONE1 TONE0 GP4C -- -- GP3C -- -- GP2C -- -- GP1C -- --
RG2PDN RG1PDN -- TX NOISE0 -- --
VOX ON LVL1 ON/OFF VOX OUT TX NOISE1
R/W: Read/Write enable
R: Read only register
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Operating Junction Temperature * Symbol VDD VAIN VDIN TSTG Tjmax Condition -- -- -- -- -- Rating -0.3 to +4.6 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 +150 Unit V V V C C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Operating Junction Temperature (Average) * Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Bypass Capacitor for SG Master Clock Frequency Bit Clock Frequency Synchronous Signal Frequency Clock Duty Ratio Sync Pulse Setting Time Synchronous Signal Width Symbol VDD Ta Tjmaxa VIH VIL tir tif CDL CSG FMCK FBCK1 FBCK2 FSYNC DCLK TSB TBS tWS Condition -- -- -- all digital input pins all digital input pins all digital input pins all digital input pins all digital output pins Between SG and AG MCK BCLK (A/-law) BCLK (linear) SYNC MCK, BCLK SYNC BCLK BCLK SYNC SYNC Min. 2.4 -40 -- 0.7 x VDD 0 -- -- -- 0.1 -0.01% 64 128 -- 40 -100 100 1BCLK Typ. -- +25 -- -- -- -- -- -- -- 2.048 -- -- 8.0 50 -- -- -- Max. 3.3 +85 105 VDD 0.20 x VDD 50 50 100 -- +0.01% 2048 2048 -- 60 100 -- 100 Unit V C C V V ns ns pF F MHz kHz kHz kHz % ns ns s
*
The device should be used in such a way that Tjmax (average) is less than 105C. Tjmax is given by the equation: Tjmax = P x ja + Ta where P = Power dissipation (W) A 48-pin TQFP package is used. ja = 195C (not mounted on a PCB, in still-air-ambient) ja = 156C (mounted on a typical PCB, in still-air-ambient) For more details, refer to PACKAGE INFORMATION DATA BOOK.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 Input Leakage Current Output High Voltage Output Low Voltage Input Capacitance IIH IIL VOH VOL CIN Condition Operating mode No signal (VDD = 3.0 V) Operating mode No signal (VDD = 3.0 V) SPO+, SPO- or EAR1, 2 is active Power down mode (VDD = 3.0 V, Ta = 25C) VI = VDD VI = 0 V IOH = 0.4 mA IOL = -1.2 mA -- Min. 0 0 0 -- -- 0.5 x VDD 0 -- Typ. 5.0 16.0 1.0 -- -- -- 0.2 5 Max. 11.0 32.0 10 2.0 1.5 VDD 0.4 -- Unit mA mA A A A V V pF
Analog Interface Characteristics
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Symbol RINX RLGX1 RLGX2 RLGX3 CLGX VO1 Output Amplitude * Condition MIC1I, MIC2I, MIC3-, MIC3+ MIC1O, MIC2O, MIC3O, EXTO EAR1O, EAR2O SPO+, SPO- differential output Analog output MIC1O, MIC2O, MIC3O, EXTO, RL = 20 k EAR1O, EAR2O, RL = 32 VO2 VO3 Total Harmonic Distortion THD VOFGX1 Offset Voltage SG Output Voltage SG Output Impedance Internal switch ON Impedance VOFGX2 VSG RSG RSW SPO+, SPO-, (Differential output) VDD = 3.0 V, RL = 8 SPO- (Single output) VDD = 3.0 V, RL = 20 k , THD = 1% EAR1O, EAR2O, SPO+, SPO- VDD = 3.0 V (at VO1, VO2) MIC1O, MIC2O, MIC3O EAR1O, EAR2O, SPO+, SPO-, EXTO SG SG All internal analog switches (1.4 V DC bias) -- 2.0 -- -40 -100 -- -- -- -- 2.6 -- -- -- 1.4 40 -- 2.6 -- 5.0 40 100 -- 80 300 VPP VPP % mV mV V k Min. 10 20 32 8 -- -- Typ. -- -- -- -- -- -- Max. -- -- -- -- 50 1.3 Unit M k pF VPP
* -7.7 dBm (600 ) = 0 dBm0, +3.17 dBm0 = 1.3 VPP
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AC Characteristics
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Condition Parameter Symbol LOSS T1 LOSS T3 LOSS T4 LOSS T5 LOSS R6 LOSS R1 Receive Frequency Response *2 LOSS R2 LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio *2 SD R2 SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking *2 GT R2 GT R3 GT R4 GT R5 1020 1020 1020 1020 Frequency (Hz) 0 to 60 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- -0.5 -1.0 -1.2 -- -0.5 -1.0 -1.2 -0.5 *1 *1 0 -- -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.5 Level (dBm0) Others Min. 25 -0.15 0 -- -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- 0.5 1.0 1.2 0.5 1.0 1.2 0.5 0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- 0.5 0.80 0.80 -- 0.20 Max. -- 0.20 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
LOSS T2 300 to 3000 Transmit Frequency Response
*1 Use the P-message weighted filter. *2 EXTO output
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AC Characteristics (Continued)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Condition Parameter Symbol Frequency (Hz) -- -- Level (dBm0) MIC1I, MIC2I, MIC3 = SG -- Others Min. Typ. Max. Unit
Idle Channel Noise
NIDLT NIDLR AVT
*1 *1,*2,*4 MIC1O, MIC2O, MIC3O EXTO
-- -- 0.285 0.285 30
-- -- 0.320 *3 0.320 *3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-68 -72 0.359 0.359 -- -- 200 200 200 200 100 -- -- -- -- -- -- -- --
dBmOp
Vrms Vrms dB dB ns ns ns ns kHz s s s s s s ns s
Absolute Signal Amplitude AVR Power Supply Noise Rejection Ratio PSRRT PSRRR tSDX tSDR Digital Input/Output Timing PCM Interface tXD1 tRD1 tXD2 tRD2 tXD3 tRD3 fSCL tBUF tHD:STA tLOW I C Interface timing
2
1020
0
Noise frequency:
Noise level:
--
0 to 50 kHz 50 mVpp
30 0
--
1 LSTTL See + Figure 6 100 pF
0 0 0 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0
tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO
--
CL = 50 pF
See Figure 7
*1 *2 *3 *4
Use the P-message weighted filter. PCMIN input code "11010101" (A-law) "11111111" (-law) 0.320 Vrms = 0 dBm0 = -7.7 dBm EXTO output
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AC Characteristics (DTMF and Other Tones)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Frequency Difference Symbol DFT VTL Original (reference) Tones Signal Level *5 VTH VRL VRH Relative Level of DTMF Tones Condition DTMF Tones, Other Tones Transmit tones DTMF (Low) and (gain setting of Other Tones 0 dB) DTMF (High) Receive tones DTMF (Low) (gain setting of DTMF (High) and -6 dB) Other Tones Min. -1.5 -18 -16 -4 -2 +1 Typ. -- -16 -14 -2 0 +2 Max. +1.5 -14 -12 0 +2 +3 Unit % dBm0 dBm0 dBm0 dBm0 dB
RDTMF VTH/VTL, VRH/VRL
*5
Not including programmable gain set values
AC Characteristics (Programmable Gain Stages)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Gain Accuracy Symbol DG Condition All gain stages, to programmed value Min. -1 Typ. 0 Max. +1 Unit dB
AC Characteristics (Voice Detect Function)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Voice Detection Time Voice Detection Accuracy Symbol TVON TVOF DVX Condition Silence Voice (Voice/silence differential: 10 dB) For detection level set values by CR6-B6 Min. -- 140 -2.5 Typ. 5 160 0 Max. -- 180 2.5 Unit ms ms dB
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AC Characteristics (General Purpose Drivers)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Output Voltage Output Load Resistance Symbol VO RO Condition IOUT = 150 mA, GP1 - GP4 Min. -- 20 Typ. -- -- Max. 0.7 -- Unit V
AC Characteristics (Regulator 1 and 2)
(VDD = 2.4 to 3.3 V, Ta = -40 to +85C) Parameter Input Voltage Output Voltage Load Current Dropout Voltage Symbol Vi1 Vi2 VO IO VDROP Condition IOUT = 50 mA IOUT = 150 mA RGIN = 3.6 V, IOUT = 0 mA, Ta = 25C 3.5 V < RGIN < 4.1 V IOUT = 150 mA , RGIN = 3.6 V IOUT = 50 mA 3.3 V < RGIN < 4.1 V, Ta = 25C RG1PDN = 0, RG2PDN = 0 Min. 3.3 3.5 2.93 -- -- -- Typ. 3.6 3.6 3.00 -- -- 0.1 0.1 Max. 4.1 4.1 3.07 150 200 1.25 10 Unit V V V mA mV %/V A
Output Voltage Line Regulation dVO/dVI Standby Current Istanby
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TIMING DIAGRAM
Transmit Side PCM Timing (Normal Synchronous Interface)
BCLK
0 1 2 3 4 5 6 7 8 9 10
tSB
tWS
SYNC
tXD1 tSDX
MSB
tXD2
tXD3
LSB
PCMOUT
When tSB >= 0, the Delay of the MSB is defined as tXD1. When tSB < 0, the Delay of the MSB is defined as tSDX.
Transmit Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0 1 2 3 4 5 6 7 8 9 10
tSB tWS
tBS tXD1
MSB
SYNC
tXD2
tXD3
LSB
PCMOUT
Receive Side PCM Timing (Normal Synchronous Interface)
BCLK
0 1 2 3 4 5 6 7 8 9 10
tSB
tWS tRD2 tSDR
MSB
SYNC
tRD1
tRD3
LSB
PCMIN
Receive Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0 1 2 3 4 5 6 7 8 9 10
tSB tWS
tBS tRD1
MSB
SYNC
tRD2
tRD3
LSB
PCMIN
Figure 6 PCM Interface Timing
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I2C Interface
SDA
tBUF tLOW fSCL tHD:STA
SCL P S tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA Sr tSU:STO P
2 Figure 7 I C Interface Timing
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FUNCTIONAL DESCRIPTION
Control Registers CR0 (Basic operating mode 1) Note: The initial value means a value set when the device is reset by the PDN pin.
B7 CR0 Initial value A/ SEL 0 B6 SPOUT PON 0 B5 PDN ALL 0 B4 PDN TX 0 B3 PDN RX 0 B2 SLP 0 B1 SLP SEL 0 B0 LNR 0
B7....... PCM interface companding law select 0: -law 1: A-law B6....... Power-on control for output amplifies (SPO+, SPO-) 0: Power down 1: Power on B5....... Power down (entire circuitry) 0: Power on 1: Power down ORed with the inverted PDN signal. When using this data, set PDN to "L". The control registers are not reset by this signal. B4....... Power down (transmit only) 0: Power on 1: Power down B3....... Power down (receive only) 0: Power on 1: Power down B2....... Slope filter enable 0: Slope filter disable 1: Slope filter enable B1....... Slope filter frequency response select 0: CASE1 1: CASE2 Either CASE1 or CASE2 can be selected in Figure 8. B0....... PCM interface linear code select 0: PCM companding law selected by CR0-B7 1: 14-bit linear code (2's complement)
6 4 2 0 -2 Gain [dB] -4 -6 -8 -10 -12 -14 0 500 1000 1500 2000 2500 Frequency [Hz] 3000 3500 4000 CASE1 CASE2
Figure 8 Slope Filter Frequency Characteristics
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CR1 (Basic operating mode 2)
B7 CR1 Initial Value MIC SEL1 0 B6 MIC SEL0 0 B5 SP SEL1 0 B4 SP SEL0 0 B3 SHORT FRAME 0 B2 -- 0 B1 SW C/A 0 B0 RX PAD 0
B7, B6..... Selection of an input amplifier to encoder (B7, B6) = (0, 0): MIC1 = (0, 1): MIC2 = (1, 0): MIC3 = (1, 1): No input Amplifiers which are not selected are powered down and their outputs go in the high impedance state. B5, B4..... Selection of an output amplifier (B5, B4) = (0, 0): EXTO = (0, 1): EAR1O = (1, 0): EAR2O = (1, 1): No output Amplifiers which are not selected are powered down and their outputs go in the high impedance state. B3 ....... Short frame synchronous interface select 0: Long frame synchronous interface, 1: Short frame synchronous interface B2 ....... Not used. When writing data, write "0". B1 ....... Analog switch control 0: The SWB pin is internally connected to the SWA pin. 1: The SWB pin is internally connected to the SWC pin. The unconnected pins go in a high impedance state. B0 ....... Receive side PAD 0: No pad 1: A pad of 12 dB loss is inserted in the receive side voice path.
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CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment)
B7 CR2 Initial Value B6 B5 B4 B3 B2 B1 B0
TX RX TX GAIN2 TX GAIN1 TX GAIN0 RX GAIN2 RX GAIN1 RX GAIN0 ON/OFF ON/OFF 0 0 1 1 0 0 1 1
B7 .................Transmit side PCM signal ON/OFF 0: ON 1: OFF B6, B5, B4.....Transmit side signal gain adjustment (refer to Table 2) B3 .................Receive side PCM signal ON/OFF 0: ON 1: OFF B2, B1, B0.....Receive side signal gain adjustment (refer to Table 2) Table 2 Transmit/Receive Gain Settings
B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit Gain -6 dB -4 dB -2 dB 0 dB +2 dB +4 dB +6 dB +8 dB B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Gain -12 dB -9 dB -6 dB -3 dB 0 dB +3 dB +6 dB +9 dB
The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. The DTMF and other tone transmit signals are enabled by CR4-B6, and the gain setting is referenced to the levels shown below. DTMF tones (low group):.............................. -16 dBm0 DTMF tones (high group) and other tones: ... -14 dBm0 For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1,1,1), then the following tones are output at the PCMOUT pin. DTMF tones (low group):.............................. -8 dBm0 DTMF tones (high group) and other tones: ... -6 dBm0 Gains of the side tone (path to receive side from transmit side) and the receive side tone can be set by register CR3.
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CR3 (Side tone and other tone generator gain setting)
B7 CR3 Initial Value B6 B5 B4 B3 TONE GAIN3 0 B2 TONE GAIN2 0 B1 TONE GAIN1 0 B0 TONE GAIN0 0
SIDE TONE SIDE TONE SIDE TONE TONE GAIN2 GAIN1 GAIN0 ON/OFF 0 0 0 0
B7, B6, B5 ......... Side tone path gain setting (refer to Table 3) B4...................... Tone generator ON/OFF 0: OFF 1: ON B3, B2, B1, B0 ... Tone generator gain adjustment for receive side (refer to Table 4) Table 3 Side Tone Gain Settings
B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Path Gain OFF -15 dB -13 dB -11 dB -9 dB -7 dB -5 dB -3 dB
Table 4 Receive Side Tone Generator Gain Settings
B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain OFF -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB
The receive side tone generator gain settings shown in Table 4 are referenced to the following levels as a reference. DTMF tones (low group):..............................+4 dBm0 DTMF tones (high group) and others tones: . +6 dBm0 For example, if the tone generator gain set value is set to -6 dB (B3, B2, B1, B0) = (1, 1, 1, 1), then tones at the following levels are output at EXTO. DTMF tone (low group): ...............................-2 dBm0 DTMF tone (high group) and other tones:..... 0 dBm0
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CR4 (Tone generator operating mode and frequency select)
B7 CR4 Initial Value DTMF/ Others SEL 0 B6 TONE SEND 0 B5 -- 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0 B1 TONE1 0 B0 TONE0 0
B7........................... DTMF or other tones select 0: Others 1: DTMF B6........................... Tone transmit enable (Transmit side) 0: Voice signal transmit 1: Tone transmit B5........................... Not used. When writing data, write "0". B4, B3, B2, B1, B0.. Tone frequency setting (refer to Tables 5-1 and 5-2) (a) B7 = 1 (DTMF tone) Table 5-1 Tone Generator Frequency Settings
B4 * * * * * * * * B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 697 Hz + 1209 Hz 697 Hz + 1336 Hz 697 Hz + 1477 Hz 697 Hz + 1633 Hz 770 Hz + 1209 Hz 770 Hz + 1336 Hz 770 Hz + 1477 Hz 770 Hz + 1633 Hz B4 * * * * * * * * B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 0 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 852 Hz + 1209 Hz 852 Hz + 1336 Hz 852 Hz + 1477 Hz 852 Hz + 1633 Hz 941 Hz + 1209 Hz 941 Hz + 1336 Hz 941 Hz + 1477 Hz 941 Hz + 1633 Hz
*Undefined
(b) B7 = 0 (Other tones) Table 5-2 Tone Generator Frequency Settings
B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 667 Hz 800 Hz 1000 Hz 400 Hz 440 Hz 480 Hz Frequency 2730 Hz/2500 Hz 8 Hz wamb. 2000 Hz/2667 Hz 8 Hz wamb. 1000 Hz/1333 Hz 8 Hz wamb. B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3000 Hz 2700 Hz 2500 Hz 2400 Hz 1477 Hz 1633 Hz 2000 Hz 2100 Hz Frequency 1200 Hz 1300 Hz
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CR5 (Regulator control, General purpose driver control)
B7 CR5 Initial Value GP1 SEL CR/TONE 0 B6 -- 0 B5 B4 B3 GP4C 0 B2 GP3C 0 B1 GP2C 0 B0 GP1C 0
RG2PDN RG1PDN 0 0
B7...................... Selection of how to control General purpose driver 1. 0: Control register CR5-B0 1: GP1 is controlled by a sign bit of the receiver. B6...................... Not used B5...................... Power down control for Regulator 2 0: Power down 1: Power on When using this data, set the RG2PDN pin at a "L" level. B4...................... Power down control for Regulator 1 0: Power down 1: Power on When using this data, set the RG1PDN pin at a "L" level. B3, B2, B1, B0 ... General purpose driver control 0: Off (high impedance) 1: On ("L" output)
CR6 (VOX function control)
B7 CR6 Initial Value VOX ON/OFF 0 B6 ON LVL1 0 B5 -- * B4 -- 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 -- 0
B7................................ Voice/silence detect function ON/ OFF 0: OFF 1: ON If B7 is set to a logic "1", B3 should be set to a logic "1". B6................................ Voice detector level setting 0: -26 dBm0 1: -38 dBm0 B5................................ Reserved bit. When writing data, write "0". B4, B3, B2, B1, B0....... Not used. When writing data, write "0". CR7 (Detect register, read only)
B7 CR7 Initial Value VOX OUT 0 B6 TX Noise Level1 0 B5 TX Noise Level0 0 B4 -- * B3 -- * B2 -- * B1 -- * B0 -- *
*Used for testing the device and undefined B7............................. Transmit side voice/silence detection 0: silence 1: voice detect B6, B5....................... Transmit side silence detect level (indicator) (0,0): Below -50 dBm0 (0,1): -40 to -50 dBm0 (1,0): -30 to -40 dBm0 (1,1): Above -30 dBm0 Note: These outputs are enabled only when the VOX (CR6-B7) = "1". B4, B3, B2, B1, B0.... Not used
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APPLICATION CIRCUIT
VDD
Mic
GND C = 1 F SWB C SWC SWA
VDD (3.0 V)
C= 10 F VDD
R C R
MIC1I R MIC1O MIC2I
20 k
Voice detect
PCM Compand
PCMOUT
20 k
A/D
C
R MIC2O
Slope Filter
BPF BCLK TONE/DTMF Gen SYNC
C C R
MIC3- MIC3+ 20 k D/A MIC3O R C SG EAR1O 32 Hands Free Kit Regulator2 (150 mA) Sign bit GP1(150 mA) GP2(150 mA) RG1IN(3.6 V) Regulator1 (150 mA) RG1O(3.0 V) RG1PDN RG2IN(3.6 V) RG2O(3.0 V) RG2PDN 20 k EAR2O 32 C Other IC + C=10F Buzzer LCD Key Pad Vibrator Other IC + C=10F LPF PCM Expand PCMIN VDD (3.6 V)
C = 1 F
Speaker Phone
IN OUT SG MCU I/F 2 (I C) 8
C=0.1F
GP3(150 mA) GP4(150 mA) AGGP
Earphone
VREF 8
EXTO
SPO+
SPO-
PDN
EXTI
SCL
R
MCK
SDA
3V R = 1k to 10 k
C
R C
Speaker
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP48-P-0707-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.13 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No.
FEDL7041-01 FEDL7041-02 FEDL7041-03
Date
Nov. 2000 Jun. 16, 2004 Nov. 2, 2005
Page Previous Current Edition Edition
8 11 17 8 11 17 24 1
st
Description
Edition
More clarification of PCMOUT output state Addition of tSB Addition of tSB Addition of description about tXD1 and tSDX Addition of description about CR6-B3
FEDL7041-04
Mar. 2, 2006
24
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2006 Oki Electric Industry Co., Ltd.
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